Although the NAND flash memory, as a main stream of nonvolatile memories currently, has advantages such as high density, low lost etc., the NAND flash memory also face some problems such as insufficient times of erasing and writing (<1e5), slow writing speed (˜1ms), high operating voltage (˜15V), and difficulty in further size reduction etc. Therefore, a new type of memory is continuously researched for substituting the NAND flash memory. The resistive-switching devices attract wide attentions from the research community and industry community due to many advantages such as sufficient times of erasing and writing (>1e9), high erasing and writing speed (˜10ns), low operating voltage (<3V), simple process, compatibility with CMOS, and convenient size reduction (with an occupied unit area of ˜4F2).
A typical structure of the resistive-switching device is a three-layer structure with an electrode, a resistive-switching layer and an electrode, which is similar to a capacitor. The resistive-switching layer may have a resistive-switching under the excitation of a voltage or a current. In terms of voltage operating modes, the resistive-switching device may operate in two operating modes, i.e., a single electrode mode and a dual electrode mode. A resistive-switching phenomenon in the single electrode mode depends on a size of voltage excitation, regardless of a direction; and a resistive-switching phenomenon in the dual electrode mode depends on a size and a direction of the applied voltage excitation. Currently, the resistive-switching device is primarily applied as a resistive-switching memory. According to the principle of the resistive-switching memory, different information is stored using different resistance values of the resistive-switching layer between two electrodes, and the stored information is rewritten by applying a voltage pulse or Direct Current (DC) sweep to the electrodes to change the resistance value of the resistive-switching layer.
In addition to the application in the resistive-switching memory, the resistive-switching device has potentials in logical devices, neuronal devices etc. due to its simple structure and excellent performance. The present disclosure proposes a method for achieving a full adder based on a cross-bar array of resistive-switching devices.
An adder is a component in a digital circuit for executing an addition operation, and is the basis of constituting an arithmetic logic unit in a core microprocessor of an electronic computer. In an electronic system, the adder is primarily responsible for calculating data such as addresses, indexes etc. In addition, the adder is also an important part of some other hardware such as a binary multiplier etc. Adders may be divided into half adders and full adders. The half adders implement an add function of two binary numbers. In addition to the function of the half adders, the full adders implement functions of carry input and carry output at each bit, so as to achieve a complete operation.
Currently, adders in the digital circuit are generally achieved using a CMOS logical circuit by means of Complementary transmission Pipe Logic (CPL), Dual transmission Pipe Logic (DPL) etc. A 1-bit adder achieved using a CMOS logic needs about 20 transistors. If a 4-bit adder or a more than 4-bit adder is to be achieved, a number of transistors which is greater than a number of linearly increased transistors is needed, an occupied chip area is large, and reduction in power consumption becomes difficult due to the use of a large number of transistors.